Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SC8280XP Mobile Display Subsystem
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc.
  15
  16 $ref: /schemas/display/msm/mdss-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sc8280xp-mdss
  21
  22   clocks:
  23     items:
  24       - description: Display AHB clock from gcc
  25       - description: Display AHB clock from dispcc
  26       - description: Display core clock
  27
  28   clock-names:
  29     items:
  30       - const: iface
  31       - const: ahb
  32       - const: core
  33
  34 patternProperties:
  35   "^display-controller@[0-9a-f]+$":
  36     type: object
  37     properties:
  38       compatible:
  39         const: qcom,sc8280xp-dpu
  40
  41   "^displayport-controller@[0-9a-f]+$":
  42     type: object
  43     properties:
  44       compatible:
  45         enum:
  46           - qcom,sc8280xp-dp
  47           - qcom,sc8280xp-edp
  48
  49 unevaluatedProperties: false
  50
  51 examples:
  52   - |
  53     #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
  54     #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
  55     #include <dt-bindings/interrupt-controller/arm-gic.h>
  56     #include <dt-bindings/interconnect/qcom,sc8280xp.h>
  57     #include <dt-bindings/power/qcom-rpmpd.h>
  58
  59     display-subsystem@ae00000 {
  60         compatible = "qcom,sc8280xp-mdss";
  61         reg = <0x0ae00000 0x1000>;
  62         reg-names = "mdss";
  63
  64         power-domains = <&dispcc0 MDSS_GDSC>;
  65
  66         clocks = <&gcc GCC_DISP_AHB_CLK>,
  67                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
  68                  <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
  69         clock-names = "iface",
  70                       "ahb",
  71                       "core";
  72
  73         resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
  74
  75         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  76         interrupt-controller;
  77         #interrupt-cells = <1>;
  78
  79         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
  80                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
  81         interconnect-names = "mdp0-mem", "mdp1-mem";
  82
  83         iommus = <&apps_smmu 0x1000 0x402>;
  84
  85         #address-cells = <1>;
  86         #size-cells = <1>;
  87         ranges;
  88
  89         display-controller@ae01000 {
  90             compatible = "qcom,sc8280xp-dpu";
  91             reg = <0x0ae01000 0x8f000>,
  92             <0x0aeb0000 0x2008>;
  93             reg-names = "mdp", "vbif";
  94
  95             clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
  96                      <&gcc GCC_DISP_SF_AXI_CLK>,
  97                      <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
  98                      <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
  99                      <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
 100                      <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
 101             clock-names = "bus",
 102                           "nrt_bus",
 103                           "iface",
 104                           "lut",
 105                           "core",
 106                           "vsync";
 107
 108             assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
 109             assigned-clock-rates = <19200000>;
 110
 111             operating-points-v2 = <&mdss0_mdp_opp_table>;
 112             power-domains = <&rpmhpd SC8280XP_MMCX>;
 113
 114             interrupt-parent = <&mdss0>;
 115             interrupts = <0>;
 116
 117             ports {
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120
 121                 port@0 {
 122                     reg = <0>;
 123                     endpoint {
 124                         remote-endpoint = <&mdss0_dp0_in>;
 125                     };
 126                 };
 127
 128                 port@4 {
 129                     reg = <4>;
 130                     endpoint {
 131                         remote-endpoint = <&mdss0_dp1_in>;
 132                     };
 133                 };
 134
 135                 port@5 {
 136                     reg = <5>;
 137                     endpoint {
 138                         remote-endpoint = <&mdss0_dp3_in>;
 139                     };
 140                 };
 141
 142                 port@6 {
 143                     reg = <6>;
 144                     endpoint {
 145                         remote-endpoint = <&mdss0_dp2_in>;
 146                     };
 147                 };
 148             };
 149         };
 150     };
 151 ...