Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DSI controller
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 properties:
  13   compatible:
  14     oneOf:
  15       - items:
  16           - enum:
  17               - qcom,apq8064-dsi-ctrl
  18               - qcom,msm8226-dsi-ctrl
  19               - qcom,msm8916-dsi-ctrl
  20               - qcom,msm8953-dsi-ctrl
  21               - qcom,msm8974-dsi-ctrl
  22               - qcom,msm8996-dsi-ctrl
  23               - qcom,msm8998-dsi-ctrl
  24               - qcom,qcm2290-dsi-ctrl
  25               - qcom,sc7180-dsi-ctrl
  26               - qcom,sc7280-dsi-ctrl
  27               - qcom,sdm660-dsi-ctrl
  28               - qcom,sdm845-dsi-ctrl
  29               - qcom,sm6115-dsi-ctrl
  30               - qcom,sm6125-dsi-ctrl
  31               - qcom,sm6350-dsi-ctrl
  32               - qcom,sm6375-dsi-ctrl
  33               - qcom,sm8150-dsi-ctrl
  34               - qcom,sm8250-dsi-ctrl
  35               - qcom,sm8350-dsi-ctrl
  36               - qcom,sm8450-dsi-ctrl
  37               - qcom,sm8550-dsi-ctrl
  38           - const: qcom,mdss-dsi-ctrl
  39       - enum:
  40           - qcom,dsi-ctrl-6g-qcm2290
  41           - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
  42         deprecated: true
  43
  44   reg:
  45     maxItems: 1
  46
  47   reg-names:
  48     const: dsi_ctrl
  49
  50   interrupts:
  51     maxItems: 1
  52
  53   clocks:
  54     description: |
  55       Several clocks are used, depending on the variant. Typical ones are::
  56        - bus:: Display AHB clock.
  57        - byte:: Display byte clock.
  58        - byte_intf:: Display byte interface clock.
  59        - core:: Display core clock.
  60        - core_mss:: Core MultiMedia SubSystem clock.
  61        - iface:: Display AXI clock.
  62        - mdp_core:: MDP Core clock.
  63        - mnoc:: MNOC clock
  64        - pixel:: Display pixel clock.
  65     minItems: 3
  66     maxItems: 9
  67
  68   clock-names:
  69     minItems: 3
  70     maxItems: 9
  71
  72   phys:
  73     maxItems: 1
  74
  75   phy-names:
  76     deprecated: true
  77     const: dsi
  78
  79   syscon-sfpb:
  80     description: A phandle to mmss_sfpb syscon node (only for DSIv2).
  81     $ref: /schemas/types.yaml#/definitions/phandle
  82
  83   qcom,dual-dsi-mode:
  84     type: boolean
  85     description: |
  86       Indicates if the DSI controller is driving a panel which needs
  87       2 DSI links.
  88
  89   qcom,master-dsi:
  90     type: boolean
  91     description: |
  92       Indicates if the DSI controller is the master DSI controller when
  93       qcom,dual-dsi-mode enabled.
  94
  95   qcom,sync-dual-dsi:
  96     type: boolean
  97     description: |
  98       Indicates if the DSI controller needs to sync the other DSI controller
  99       with MIPI DCS commands when qcom,dual-dsi-mode enabled.
 100
 101   assigned-clocks:
 102     minItems: 2
 103     maxItems: 4
 104     description: |
 105       Parents of "byte" and "pixel" for the given platform.
 106       For DSIv2 platforms this should contain "byte", "esc", "src" and
 107       "pixel_src" clocks.
 108
 109   assigned-clock-parents:
 110     minItems: 2
 111     maxItems: 4
 112     description: |
 113       The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
 114
 115   power-domains:
 116     maxItems: 1
 117
 118   operating-points-v2: true
 119
 120   opp-table:
 121     type: object
 122
 123   ports:
 124     $ref: /schemas/graph.yaml#/properties/ports
 125     description: |
 126       Contains DSI controller input and output ports as children, each
 127       containing one endpoint subnode.
 128
 129     properties:
 130       port@0:
 131         $ref: /schemas/graph.yaml#/$defs/port-base
 132         unevaluatedProperties: false
 133         description: |
 134           Input endpoints of the controller.
 135         properties:
 136           endpoint:
 137             $ref: /schemas/media/video-interfaces.yaml#
 138             unevaluatedProperties: false
 139             properties:
 140               data-lanes:
 141                 maxItems: 4
 142                 minItems: 1
 143                 items:
 144                   enum: [ 0, 1, 2, 3 ]
 145
 146       port@1:
 147         $ref: /schemas/graph.yaml#/$defs/port-base
 148         unevaluatedProperties: false
 149         description: |
 150           Output endpoints of the controller.
 151         properties:
 152           endpoint:
 153             $ref: /schemas/media/video-interfaces.yaml#
 154             unevaluatedProperties: false
 155             properties:
 156               data-lanes:
 157                 maxItems: 4
 158                 minItems: 1
 159                 items:
 160                   enum: [ 0, 1, 2, 3 ]
 161
 162     required:
 163       - port@0
 164       - port@1
 165
 166   avdd-supply:
 167     description:
 168       Phandle to vdd regulator device node
 169
 170   refgen-supply:
 171     description:
 172       Phandle to REFGEN regulator device node
 173
 174   vcca-supply:
 175     description:
 176       Phandle to vdd regulator device node
 177
 178   vdd-supply:
 179     description:
 180       VDD regulator
 181
 182   vddio-supply:
 183     description:
 184       VDD-IO regulator
 185
 186   vdda-supply:
 187     description:
 188       VDDA regulator
 189
 190 required:
 191   - compatible
 192   - reg
 193   - reg-names
 194   - interrupts
 195   - clocks
 196   - clock-names
 197   - phys
 198   - assigned-clocks
 199   - assigned-clock-parents
 200   - ports
 201
 202 allOf:
 203   - $ref: ../dsi-controller.yaml#
 204   - if:
 205       properties:
 206         compatible:
 207           contains:
 208             enum:
 209               - qcom,apq8064-dsi-ctrl
 210     then:
 211       properties:
 212         clocks:
 213           maxItems: 7
 214         clock-names:
 215           items:
 216             - const: iface
 217             - const: bus
 218             - const: core_mmss
 219             - const: src
 220             - const: byte
 221             - const: pixel
 222             - const: core
 223
 224   - if:
 225       properties:
 226         compatible:
 227           contains:
 228             enum:
 229               - qcom,msm8916-dsi-ctrl
 230     then:
 231       properties:
 232         clocks:
 233           maxItems: 6
 234         clock-names:
 235           items:
 236             - const: mdp_core
 237             - const: iface
 238             - const: bus
 239             - const: byte
 240             - const: pixel
 241             - const: core
 242
 243   - if:
 244       properties:
 245         compatible:
 246           contains:
 247             enum:
 248               - qcom,msm8953-dsi-ctrl
 249     then:
 250       properties:
 251         clocks:
 252           maxItems: 6
 253         clock-names:
 254           items:
 255             - const: mdp_core
 256             - const: iface
 257             - const: bus
 258             - const: byte
 259             - const: pixel
 260             - const: core
 261
 262   - if:
 263       properties:
 264         compatible:
 265           contains:
 266             enum:
 267               - qcom,msm8226-dsi-ctrl
 268               - qcom,msm8974-dsi-ctrl
 269     then:
 270       properties:
 271         clocks:
 272           maxItems: 7
 273         clock-names:
 274           items:
 275             - const: mdp_core
 276             - const: iface
 277             - const: bus
 278             - const: byte
 279             - const: pixel
 280             - const: core
 281             - const: core_mmss
 282
 283   - if:
 284       properties:
 285         compatible:
 286           contains:
 287             enum:
 288               - qcom,msm8996-dsi-ctrl
 289     then:
 290       properties:
 291         clocks:
 292           maxItems: 7
 293         clock-names:
 294           items:
 295             - const: mdp_core
 296             - const: byte
 297             - const: iface
 298             - const: bus
 299             - const: core_mmss
 300             - const: pixel
 301             - const: core
 302
 303   - if:
 304       properties:
 305         compatible:
 306           contains:
 307             enum:
 308               - qcom,msm8998-dsi-ctrl
 309               - qcom,sm6125-dsi-ctrl
 310               - qcom,sm6350-dsi-ctrl
 311     then:
 312       properties:
 313         clocks:
 314           maxItems: 6
 315         clock-names:
 316           items:
 317             - const: byte
 318             - const: byte_intf
 319             - const: pixel
 320             - const: core
 321             - const: iface
 322             - const: bus
 323
 324   - if:
 325       properties:
 326         compatible:
 327           contains:
 328             enum:
 329               - qcom,sc7180-dsi-ctrl
 330               - qcom,sc7280-dsi-ctrl
 331               - qcom,sm8150-dsi-ctrl
 332               - qcom,sm8250-dsi-ctrl
 333               - qcom,sm8350-dsi-ctrl
 334               - qcom,sm8450-dsi-ctrl
 335               - qcom,sm8550-dsi-ctrl
 336     then:
 337       properties:
 338         clocks:
 339           maxItems: 6
 340         clock-names:
 341           items:
 342             - const: byte
 343             - const: byte_intf
 344             - const: pixel
 345             - const: core
 346             - const: iface
 347             - const: bus
 348
 349   - if:
 350       properties:
 351         compatible:
 352           contains:
 353             enum:
 354               - qcom,sdm660-dsi-ctrl
 355     then:
 356       properties:
 357         clocks:
 358           maxItems: 9
 359         clock-names:
 360           items:
 361             - const: mdp_core
 362             - const: byte
 363             - const: byte_intf
 364             - const: mnoc
 365             - const: iface
 366             - const: bus
 367             - const: core_mmss
 368             - const: pixel
 369             - const: core
 370
 371   - if:
 372       properties:
 373         compatible:
 374           contains:
 375             enum:
 376               - qcom,sdm845-dsi-ctrl
 377               - qcom,sm6115-dsi-ctrl
 378               - qcom,sm6375-dsi-ctrl
 379     then:
 380       properties:
 381         clocks:
 382           maxItems: 6
 383         clock-names:
 384           items:
 385             - const: byte
 386             - const: byte_intf
 387             - const: pixel
 388             - const: core
 389             - const: iface
 390             - const: bus
 391
 392 unevaluatedProperties: false
 393
 394 examples:
 395   - |
 396      #include <dt-bindings/interrupt-controller/arm-gic.h>
 397      #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 398      #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 399      #include <dt-bindings/power/qcom-rpmpd.h>
 400
 401      dsi@ae94000 {
 402            compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 403            reg = <0x0ae94000 0x400>;
 404            reg-names = "dsi_ctrl";
 405
 406            #address-cells = <1>;
 407            #size-cells = <0>;
 408
 409            interrupt-parent = <&mdss>;
 410            interrupts = <4>;
 411
 412            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 413                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 414                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 415                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 416                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
 417                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
 418            clock-names = "byte",
 419                          "byte_intf",
 420                          "pixel",
 421                          "core",
 422                          "iface",
 423                          "bus";
 424
 425            phys = <&dsi0_phy>;
 426            phy-names = "dsi";
 427
 428            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 429            assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
 430
 431            power-domains = <&rpmhpd SC7180_CX>;
 432            operating-points-v2 = <&dsi_opp_table>;
 433
 434            ports {
 435                   #address-cells = <1>;
 436                   #size-cells = <0>;
 437
 438                   port@0 {
 439                           reg = <0>;
 440                           dsi0_in: endpoint {
 441                                    remote-endpoint = <&dpu_intf1_out>;
 442                           };
 443                   };
 444
 445                   port@1 {
 446                           reg = <1>;
 447                           dsi0_out: endpoint {
 448                                    remote-endpoint = <&sn65dsi86_in>;
 449                                    data-lanes = <0 1 2 3>;
 450                           };
 451                   };
 452            };
 453      };
 454 ...