1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: "../dsi-controller.yaml#"
19 - qcom,dsi-ctrl-6g-qcm2290
32 - description: Display byte clock
33 - description: Display byte interface clock
34 - description: Display pixel clock
35 - description: Display escape clock
36 - description: Display AHB clock
37 - description: Display AXI clock
54 "#address-cells": true
59 description: A phandle to mmss_sfpb syscon node (only for DSIv2).
60 $ref: "/schemas/types.yaml#/definitions/phandle"
65 Indicates if the DSI controller is driving a panel which needs
72 Parents of "byte" and "pixel" for the given platform.
74 assigned-clock-parents:
78 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
83 operating-points-v2: true
86 $ref: "/schemas/graph.yaml#/properties/ports"
88 Contains DSI controller input and output ports as children, each
89 containing one endpoint subnode.
93 $ref: "/schemas/graph.yaml#/$defs/port-base"
94 unevaluatedProperties: false
96 Input endpoints of the controller.
99 $ref: /schemas/media/video-interfaces.yaml#
100 unevaluatedProperties: false
109 $ref: "/schemas/graph.yaml#/$defs/port-base"
110 unevaluatedProperties: false
112 Output endpoints of the controller.
115 $ref: /schemas/media/video-interfaces.yaml#
116 unevaluatedProperties: false
138 - assigned-clock-parents
140 - operating-points-v2
143 additionalProperties: false
147 #include <dt-bindings/interrupt-controller/arm-gic.h>
148 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
149 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
150 #include <dt-bindings/power/qcom-rpmpd.h>
153 compatible = "qcom,mdss-dsi-ctrl";
154 reg = <0x0ae94000 0x400>;
155 reg-names = "dsi_ctrl";
157 #address-cells = <1>;
160 interrupt-parent = <&mdss>;
163 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
164 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
165 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
166 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
167 <&dispcc DISP_CC_MDSS_AHB_CLK>,
168 <&dispcc DISP_CC_MDSS_AXI_CLK>;
169 clock-names = "byte",
179 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
180 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
182 power-domains = <&rpmhpd SC7180_CX>;
183 operating-points-v2 = <&dsi_opp_table>;
186 #address-cells = <1>;
192 remote-endpoint = <&dpu_intf1_out>;
199 remote-endpoint = <&sn65dsi86_in>;
200 data-lanes = <0 1 2 3>;