1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SDM845 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SDM845 target.
20 - const: qcom,sdm845-mdss
33 - description: Display AHB clock from gcc
34 - description: Display core clock
44 interrupt-controller: true
46 "#address-cells": true
55 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
56 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
62 - description: MDSS_CORE reset
65 "^display-controller@[0-9a-f]+$":
67 description: Node containing the properties of DPU.
68 additionalProperties: false
73 - const: qcom,sdm845-dpu
77 - description: Address offset and size for mdp register set
78 - description: Address offset and size for vbif register set
87 - description: Display ahb clock
88 - description: Display axi clock
89 - description: Display core clock
90 - description: Display vsync clock
105 operating-points-v2: true
110 $ref: /schemas/graph.yaml#/properties/ports
112 Contains the list of output ports from DPU device. These ports
113 connect to interfaces that are external to the DPU hardware,
114 such as DSI, DP etc. Each output port contains an endpoint that
115 describes how it is connected to an external interface.
119 $ref: /schemas/graph.yaml#/properties/port
120 description: DPU_INTF1 (DSI1)
123 $ref: /schemas/graph.yaml#/properties/port
124 description: DPU_INTF2 (DSI2)
137 - operating-points-v2
147 - interrupt-controller
151 additionalProperties: false
155 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
156 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
157 #include <dt-bindings/interrupt-controller/arm-gic.h>
158 #include <dt-bindings/power/qcom-rpmpd.h>
160 display-subsystem@ae00000 {
161 #address-cells = <1>;
163 compatible = "qcom,sdm845-mdss";
164 reg = <0x0ae00000 0x1000>;
166 power-domains = <&dispcc MDSS_GDSC>;
168 clocks = <&gcc GCC_DISP_AHB_CLK>,
169 <&dispcc DISP_CC_MDSS_MDP_CLK>;
170 clock-names = "iface", "core";
172 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
173 interrupt-controller;
174 #interrupt-cells = <1>;
176 iommus = <&apps_smmu 0x880 0x8>,
177 <&apps_smmu 0xc80 0x8>;
180 display-controller@ae01000 {
181 compatible = "qcom,sdm845-dpu";
182 reg = <0x0ae01000 0x8f000>,
184 reg-names = "mdp", "vbif";
186 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
187 <&dispcc DISP_CC_MDSS_AXI_CLK>,
188 <&dispcc DISP_CC_MDSS_MDP_CLK>,
189 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
190 clock-names = "iface", "bus", "core", "vsync";
192 interrupt-parent = <&mdss>;
194 power-domains = <&rpmhpd SDM845_CX>;
195 operating-points-v2 = <&mdp_opp_table>;
198 #address-cells = <1>;
203 dpu_intf1_out: endpoint {
204 remote-endpoint = <&dsi0_in>;
210 dpu_intf2_out: endpoint {
211 remote-endpoint = <&dsi1_in>;