Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DPU dt properties for SDM845 target
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 description: |
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS and DPU are mentioned for SDM845 target.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: qcom,sdm845-mdss
  21
  22   reg:
  23     maxItems: 1
  24
  25   reg-names:
  26     const: mdss
  27
  28   power-domains:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: Display AHB clock from gcc
  34       - description: Display core clock
  35
  36   clock-names:
  37     items:
  38       - const: iface
  39       - const: core
  40
  41   interrupts:
  42     maxItems: 1
  43
  44   interrupt-controller: true
  45
  46   "#address-cells": true
  47
  48   "#size-cells": true
  49
  50   "#interrupt-cells":
  51     const: 1
  52
  53   iommus:
  54     items:
  55       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
  56       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
  57
  58   ranges: true
  59
  60   resets:
  61     items:
  62       - description: MDSS_CORE reset
  63
  64 patternProperties:
  65   "^display-controller@[0-9a-f]+$":
  66     type: object
  67     description: Node containing the properties of DPU.
  68
  69     properties:
  70       compatible:
  71         items:
  72           - const: qcom,sdm845-dpu
  73
  74       reg:
  75         items:
  76           - description: Address offset and size for mdp register set
  77           - description: Address offset and size for vbif register set
  78
  79       reg-names:
  80         items:
  81           - const: mdp
  82           - const: vbif
  83
  84       clocks:
  85         items:
  86           - description: Display ahb clock
  87           - description: Display axi clock
  88           - description: Display core clock
  89           - description: Display vsync clock
  90
  91       clock-names:
  92         items:
  93           - const: iface
  94           - const: bus
  95           - const: core
  96           - const: vsync
  97
  98       interrupts:
  99         maxItems: 1
 100
 101       power-domains:
 102         maxItems: 1
 103
 104       operating-points-v2: true
 105       ports:
 106         $ref: /schemas/graph.yaml#/properties/ports
 107         description: |
 108           Contains the list of output ports from DPU device. These ports
 109           connect to interfaces that are external to the DPU hardware,
 110           such as DSI, DP etc. Each output port contains an endpoint that
 111           describes how it is connected to an external interface.
 112
 113         properties:
 114           port@0:
 115             $ref: /schemas/graph.yaml#/properties/port
 116             description: DPU_INTF1 (DSI1)
 117
 118           port@1:
 119             $ref: /schemas/graph.yaml#/properties/port
 120             description: DPU_INTF2 (DSI2)
 121
 122         required:
 123           - port@0
 124           - port@1
 125
 126     required:
 127       - compatible
 128       - reg
 129       - reg-names
 130       - clocks
 131       - interrupts
 132       - power-domains
 133       - operating-points-v2
 134       - ports
 135
 136 required:
 137   - compatible
 138   - reg
 139   - reg-names
 140   - power-domains
 141   - clocks
 142   - interrupts
 143   - interrupt-controller
 144   - iommus
 145   - ranges
 146
 147 additionalProperties: false
 148
 149 examples:
 150   - |
 151     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 152     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 153     #include <dt-bindings/interrupt-controller/arm-gic.h>
 154     #include <dt-bindings/power/qcom-rpmpd.h>
 155
 156     display-subsystem@ae00000 {
 157           #address-cells = <1>;
 158           #size-cells = <1>;
 159           compatible = "qcom,sdm845-mdss";
 160           reg = <0x0ae00000 0x1000>;
 161           reg-names = "mdss";
 162           power-domains = <&dispcc MDSS_GDSC>;
 163
 164           clocks = <&gcc GCC_DISP_AHB_CLK>,
 165                    <&dispcc DISP_CC_MDSS_MDP_CLK>;
 166           clock-names = "iface", "core";
 167
 168           interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 169           interrupt-controller;
 170           #interrupt-cells = <1>;
 171
 172           iommus = <&apps_smmu 0x880 0x8>,
 173                    <&apps_smmu 0xc80 0x8>;
 174           ranges;
 175
 176           display-controller@ae01000 {
 177                     compatible = "qcom,sdm845-dpu";
 178                     reg = <0x0ae01000 0x8f000>,
 179                           <0x0aeb0000 0x2008>;
 180                     reg-names = "mdp", "vbif";
 181
 182                     clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 183                              <&dispcc DISP_CC_MDSS_AXI_CLK>,
 184                              <&dispcc DISP_CC_MDSS_MDP_CLK>,
 185                              <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 186                     clock-names = "iface", "bus", "core", "vsync";
 187
 188                     interrupt-parent = <&mdss>;
 189                     interrupts = <0>;
 190                     power-domains = <&rpmhpd SDM845_CX>;
 191                     operating-points-v2 = <&mdp_opp_table>;
 192
 193                     ports {
 194                            #address-cells = <1>;
 195                            #size-cells = <0>;
 196
 197                            port@0 {
 198                                    reg = <0>;
 199                                    dpu_intf1_out: endpoint {
 200                                                   remote-endpoint = <&dsi0_in>;
 201                                    };
 202                            };
 203
 204                            port@1 {
 205                                    reg = <1>;
 206                                    dpu_intf2_out: endpoint {
 207                                                   remote-endpoint = <&dsi1_in>;
 208                                    };
 209                            };
 210                     };
 211           };
 212     };
 213 ...