1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SDM845 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SDM845 target.
20 - const: qcom,sdm845-mdss
33 - description: Display AHB clock from gcc
34 - description: Display core clock
44 interrupt-controller: true
46 "#address-cells": true
55 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
56 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
62 - description: MDSS_CORE reset
65 "^display-controller@[0-9a-f]+$":
67 description: Node containing the properties of DPU.
72 - const: qcom,sdm845-dpu
76 - description: Address offset and size for mdp register set
77 - description: Address offset and size for vbif register set
86 - description: Display ahb clock
87 - description: Display axi clock
88 - description: Display core clock
89 - description: Display vsync clock
104 operating-points-v2: true
106 $ref: /schemas/graph.yaml#/properties/ports
108 Contains the list of output ports from DPU device. These ports
109 connect to interfaces that are external to the DPU hardware,
110 such as DSI, DP etc. Each output port contains an endpoint that
111 describes how it is connected to an external interface.
115 $ref: /schemas/graph.yaml#/properties/port
116 description: DPU_INTF1 (DSI1)
119 $ref: /schemas/graph.yaml#/properties/port
120 description: DPU_INTF2 (DSI2)
133 - operating-points-v2
143 - interrupt-controller
147 additionalProperties: false
151 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
152 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
153 #include <dt-bindings/interrupt-controller/arm-gic.h>
154 #include <dt-bindings/power/qcom-rpmpd.h>
156 display-subsystem@ae00000 {
157 #address-cells = <1>;
159 compatible = "qcom,sdm845-mdss";
160 reg = <0x0ae00000 0x1000>;
162 power-domains = <&dispcc MDSS_GDSC>;
164 clocks = <&gcc GCC_DISP_AHB_CLK>,
165 <&dispcc DISP_CC_MDSS_MDP_CLK>;
166 clock-names = "iface", "core";
168 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
172 iommus = <&apps_smmu 0x880 0x8>,
173 <&apps_smmu 0xc80 0x8>;
176 display-controller@ae01000 {
177 compatible = "qcom,sdm845-dpu";
178 reg = <0x0ae01000 0x8f000>,
180 reg-names = "mdp", "vbif";
182 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
183 <&dispcc DISP_CC_MDSS_AXI_CLK>,
184 <&dispcc DISP_CC_MDSS_MDP_CLK>,
185 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
186 clock-names = "iface", "bus", "core", "vsync";
188 interrupt-parent = <&mdss>;
190 power-domains = <&rpmhpd SDM845_CX>;
191 operating-points-v2 = <&mdp_opp_table>;
194 #address-cells = <1>;
199 dpu_intf1_out: endpoint {
200 remote-endpoint = <&dsi0_in>;
206 dpu_intf2_out: endpoint {
207 remote-endpoint = <&dsi1_in>;