Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DPU dt properties for SDM845 target
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 description: |
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS and DPU are mentioned for SDM845 target.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: qcom,sdm845-mdss
  21
  22   reg:
  23     maxItems: 1
  24
  25   reg-names:
  26     const: mdss
  27
  28   power-domains:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: Display AHB clock from gcc
  34       - description: Display core clock
  35
  36   clock-names:
  37     items:
  38       - const: iface
  39       - const: core
  40
  41   interrupts:
  42     maxItems: 1
  43
  44   interrupt-controller: true
  45
  46   "#address-cells": true
  47
  48   "#size-cells": true
  49
  50   "#interrupt-cells":
  51     const: 1
  52
  53   iommus:
  54     items:
  55       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
  56       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
  57
  58   ranges: true
  59
  60   resets:
  61     items:
  62       - description: MDSS_CORE reset
  63
  64 patternProperties:
  65   "^display-controller@[0-9a-f]+$":
  66     type: object
  67     description: Node containing the properties of DPU.
  68     additionalProperties: false
  69
  70     properties:
  71       compatible:
  72         items:
  73           - const: qcom,sdm845-dpu
  74
  75       reg:
  76         items:
  77           - description: Address offset and size for mdp register set
  78           - description: Address offset and size for vbif register set
  79
  80       reg-names:
  81         items:
  82           - const: mdp
  83           - const: vbif
  84
  85       clocks:
  86         items:
  87           - description: Display ahb clock
  88           - description: Display axi clock
  89           - description: Display core clock
  90           - description: Display vsync clock
  91
  92       clock-names:
  93         items:
  94           - const: iface
  95           - const: bus
  96           - const: core
  97           - const: vsync
  98
  99       interrupts:
 100         maxItems: 1
 101
 102       power-domains:
 103         maxItems: 1
 104
 105       operating-points-v2: true
 106       opp-table:
 107         type: object
 108
 109       ports:
 110         $ref: /schemas/graph.yaml#/properties/ports
 111         description: |
 112           Contains the list of output ports from DPU device. These ports
 113           connect to interfaces that are external to the DPU hardware,
 114           such as DSI, DP etc. Each output port contains an endpoint that
 115           describes how it is connected to an external interface.
 116
 117         properties:
 118           port@0:
 119             $ref: /schemas/graph.yaml#/properties/port
 120             description: DPU_INTF1 (DSI1)
 121
 122           port@1:
 123             $ref: /schemas/graph.yaml#/properties/port
 124             description: DPU_INTF2 (DSI2)
 125
 126         required:
 127           - port@0
 128           - port@1
 129
 130     required:
 131       - compatible
 132       - reg
 133       - reg-names
 134       - clocks
 135       - interrupts
 136       - power-domains
 137       - operating-points-v2
 138       - ports
 139
 140 required:
 141   - compatible
 142   - reg
 143   - reg-names
 144   - power-domains
 145   - clocks
 146   - interrupts
 147   - interrupt-controller
 148   - iommus
 149   - ranges
 150
 151 additionalProperties: false
 152
 153 examples:
 154   - |
 155     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 156     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 157     #include <dt-bindings/interrupt-controller/arm-gic.h>
 158     #include <dt-bindings/power/qcom-rpmpd.h>
 159
 160     display-subsystem@ae00000 {
 161           #address-cells = <1>;
 162           #size-cells = <1>;
 163           compatible = "qcom,sdm845-mdss";
 164           reg = <0x0ae00000 0x1000>;
 165           reg-names = "mdss";
 166           power-domains = <&dispcc MDSS_GDSC>;
 167
 168           clocks = <&gcc GCC_DISP_AHB_CLK>,
 169                    <&dispcc DISP_CC_MDSS_MDP_CLK>;
 170           clock-names = "iface", "core";
 171
 172           interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 173           interrupt-controller;
 174           #interrupt-cells = <1>;
 175
 176           iommus = <&apps_smmu 0x880 0x8>,
 177                    <&apps_smmu 0xc80 0x8>;
 178           ranges;
 179
 180           display-controller@ae01000 {
 181                     compatible = "qcom,sdm845-dpu";
 182                     reg = <0x0ae01000 0x8f000>,
 183                           <0x0aeb0000 0x2008>;
 184                     reg-names = "mdp", "vbif";
 185
 186                     clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 187                              <&dispcc DISP_CC_MDSS_AXI_CLK>,
 188                              <&dispcc DISP_CC_MDSS_MDP_CLK>,
 189                              <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 190                     clock-names = "iface", "bus", "core", "vsync";
 191
 192                     interrupt-parent = <&mdss>;
 193                     interrupts = <0>;
 194                     power-domains = <&rpmhpd SDM845_CX>;
 195                     operating-points-v2 = <&mdp_opp_table>;
 196
 197                     ports {
 198                            #address-cells = <1>;
 199                            #size-cells = <0>;
 200
 201                            port@0 {
 202                                    reg = <0>;
 203                                    dpu_intf1_out: endpoint {
 204                                                   remote-endpoint = <&dsi0_in>;
 205                                    };
 206                            };
 207
 208                            port@1 {
 209                                    reg = <1>;
 210                                    dpu_intf2_out: endpoint {
 211                                                   remote-endpoint = <&dsi1_in>;
 212                                    };
 213                            };
 214                     };
 215           };
 216     };
 217 ...