1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for MSM8998 target
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for MSM8998 target.
20 - const: qcom,msm8998-mdss
33 - description: Display AHB clock
34 - description: Display AXI clock
35 - description: Display core clock
46 interrupt-controller: true
48 "#address-cells": true
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
62 "^display-controller@[0-9a-f]+$":
64 description: Node containing the properties of DPU.
69 - const: qcom,msm8998-dpu
73 - description: Address offset and size for mdp register set
74 - description: Address offset and size for regdma register set
75 - description: Address offset and size for vbif register set
76 - description: Address offset and size for non-realtime vbif register set
87 - description: Display ahb clock
88 - description: Display axi clock
89 - description: Display mem-noc clock
90 - description: Display core clock
91 - description: Display vsync clock
107 operating-points-v2: true
109 $ref: /schemas/graph.yaml#/properties/ports
111 Contains the list of output ports from DPU device. These ports
112 connect to interfaces that are external to the DPU hardware,
113 such as DSI, DP etc. Each output port contains an endpoint that
114 describes how it is connected to an external interface.
118 $ref: /schemas/graph.yaml#/properties/port
119 description: DPU_INTF1 (DSI1)
122 $ref: /schemas/graph.yaml#/properties/port
123 description: DPU_INTF2 (DSI2)
136 - operating-points-v2
146 - interrupt-controller
150 additionalProperties: false
154 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
155 #include <dt-bindings/interrupt-controller/arm-gic.h>
156 #include <dt-bindings/power/qcom-rpmpd.h>
158 mdss: display-subsystem@c900000 {
159 compatible = "qcom,msm8998-mdss";
160 reg = <0x0c900000 0x1000>;
163 clocks = <&mmcc MDSS_AHB_CLK>,
164 <&mmcc MDSS_AXI_CLK>,
165 <&mmcc MDSS_MDP_CLK>;
166 clock-names = "iface", "bus", "core";
168 #address-cells = <1>;
169 #interrupt-cells = <1>;
172 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
173 interrupt-controller;
174 iommus = <&mmss_smmu 0>;
176 power-domains = <&mmcc MDSS_GDSC>;
179 display-controller@c901000 {
180 compatible = "qcom,msm8998-dpu";
181 reg = <0x0c901000 0x8f000>,
185 reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
187 clocks = <&mmcc MDSS_AHB_CLK>,
188 <&mmcc MDSS_AXI_CLK>,
189 <&mmcc MNOC_AHB_CLK>,
190 <&mmcc MDSS_MDP_CLK>,
191 <&mmcc MDSS_VSYNC_CLK>;
192 clock-names = "iface", "bus", "mnoc", "core", "vsync";
194 interrupt-parent = <&mdss>;
196 operating-points-v2 = <&mdp_opp_table>;
197 power-domains = <&rpmpd MSM8998_VDDMX>;
200 #address-cells = <1>;
205 dpu_intf1_out: endpoint {
206 remote-endpoint = <&dsi0_in>;
212 dpu_intf2_out: endpoint {
213 remote-endpoint = <&dsi1_in>;