1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 DWC HDMI TX Encoder
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
14 with a companion PHY IP.
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
35 $ref: /schemas/types.yaml#/definitions/phandle
37 The HDMI DDC bus can be connected to either a system I2C master or the
38 functionally-reduced I2C master contained in the DWC HDMI. When connected
39 to a system I2C master this property contains a phandle to that I2C
43 $ref: /schemas/types.yaml#/definitions/phandle
45 phandle to the iomuxc-gpr region containing the HDMI multiplexer control
49 $ref: /schemas/graph.yaml#/properties/ports
51 This device has four video ports, corresponding to the four inputs of the
52 HDMI multiplexer. Each port shall have a single endpoint.
56 $ref: /schemas/graph.yaml#/properties/port
57 description: First input of the HDMI multiplexer
60 $ref: /schemas/graph.yaml#/properties/port
61 description: Second input of the HDMI multiplexer
64 $ref: /schemas/graph.yaml#/properties/port
65 description: Third input of the HDMI multiplexer
68 $ref: /schemas/graph.yaml#/properties/port
69 description: Fourth input of the HDMI multiplexer
90 unevaluatedProperties: false
94 #include <dt-bindings/clock/imx6qdl-clock.h>
97 reg = <0x00120000 0x9000>;
98 interrupts = <0 115 0x04>;
100 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
101 <&clks IMX6QDL_CLK_HDMI_ISFR>;
102 clock-names = "iahb", "isfr";
105 #address-cells = <1>;
111 hdmi_mux_0: endpoint {
112 remote-endpoint = <&ipu1_di0_hdmi>;
119 hdmi_mux_1: endpoint {
120 remote-endpoint = <&ipu1_di1_hdmi>;