1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 Clock and Reset Unit
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3399 clock controller generates and supplies clock to various
15 controllers within the SoC and also implements a reset controller for SoC
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. All available clocks are defined as
19 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
20 used in device tree sources. Similar macros exist for the reset sources in
22 There are several clocks that are generated outside the SoC. It is expected
23 that they are defined using standard clock bindings with following
25 - "xin24m" - crystal input - required,
26 - "xin32k" - rtc clock - optional,
27 - "clkin_gmac" - external GMAC clock - optional,
28 - "clkin_i2s" - external I2S clock - optional,
29 - "pclkin_cif" - external ISP clock - optional,
30 - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
31 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
36 - rockchip,rk3399-pmucru
55 $ref: /schemas/types.yaml#/definitions/phandle
57 Phandle to the syscon managing the "general register files". It is used
58 for GRF muxes, if missing any muxes present in the GRF will not be
67 additionalProperties: false
71 pmucru: clock-controller@ff750000 {
72 compatible = "rockchip,rk3399-pmucru";
73 reg = <0xff750000 0x1000>;
78 cru: clock-controller@ff760000 {
79 compatible = "rockchip,rk3399-cru";
80 reg = <0xff760000 0x1000>;