1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8450
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains on SM8450.
17 include/dt-bindings/clock/qcom,sm8450-dispcc.h
27 - description: Board XO source
28 - description: Board Always On XO source
29 - description: Display's AHB clock
30 - description: sleep clock
31 - description: Byte clock from DSI PHY0
32 - description: Pixel clock from DSI PHY0
33 - description: Byte clock from DSI PHY1
34 - description: Pixel clock from DSI PHY1
35 - description: Link clock from DP PHY0
36 - description: VCO DIV clock from DP PHY0
37 - description: Link clock from DP PHY1
38 - description: VCO DIV clock from DP PHY1
39 - description: Link clock from DP PHY2
40 - description: VCO DIV clock from DP PHY2
41 - description: Link clock from DP PHY3
42 - description: VCO DIV clock from DP PHY3
50 '#power-domain-cells':
58 A phandle and PM domain specifier for the MMCX power domain.
63 A phandle to an OPP node describing required MMCX performance point.
72 - '#power-domain-cells'
74 additionalProperties: false
78 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
79 #include <dt-bindings/clock/qcom,rpmh.h>
80 #include <dt-bindings/power/qcom-rpmpd.h>
81 clock-controller@af00000 {
82 compatible = "qcom,sm8450-dispcc";
83 reg = <0x0af00000 0x10000>;
84 clocks = <&rpmhcc RPMH_CXO_CLK>,
85 <&rpmhcc RPMH_CXO_CLK_A>,
86 <&gcc GCC_DISP_AHB_CLK>,
94 #power-domain-cells = <1>;
95 power-domains = <&rpmhpd SM8450_MMCX>;
96 required-opps = <&rpmhpd_opp_low_svs>;