1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SC7280
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains on SC7280.
16 See also dt-bindings/clock/qcom,dispcc-sc7280.h.
20 const: qcom,sc7280-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
27 - description: Pixel clock from DSI PHY
28 - description: Link clock from DP PHY
29 - description: VCO DIV clock from DP PHY
30 - description: Link clock from EDP PHY
31 - description: VCO DIV clock from EDP PHY
36 - const: gcc_disp_gpll0_clk
37 - const: dsi0_phy_pll_out_byteclk
38 - const: dsi0_phy_pll_out_dsiclk
39 - const: dp_phy_pll_link_clk
40 - const: dp_phy_pll_vco_div_clk
41 - const: edp_phy_pll_link_clk
42 - const: edp_phy_pll_vco_div_clk
50 '#power-domain-cells':
63 - '#power-domain-cells'
65 additionalProperties: false
69 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
70 #include <dt-bindings/clock/qcom,rpmh.h>
71 clock-controller@af00000 {
72 compatible = "qcom,sc7280-dispcc";
73 reg = <0x0af00000 0x200000>;
74 clocks = <&rpmhcc RPMH_CXO_CLK>,
75 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
82 clock-names = "bi_tcxo",
84 "dsi0_phy_pll_out_byteclk",
85 "dsi0_phy_pll_out_dsiclk",
86 "dp_phy_pll_link_clk",
87 "dp_phy_pll_vco_div_clk",
88 "edp_phy_pll_link_clk",
89 "edp_phy_pll_vco_div_clk";
92 #power-domain-cells = <1>;