1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller Binding
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm multimedia clock control module which supports the clocks, resets and
47 '#power-domain-cells':
55 Protected clock specifier list as per common clock binding
59 Regulator supply for the GPU_GX GDSC
66 - '#power-domain-cells'
68 additionalProperties: false
82 - description: Board PXO source
83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
85 - description: DSI phy instance 1 dsi clock
86 - description: DSI phy instance 1 byte clock
87 - description: DSI phy instance 2 dsi clock
88 - description: DSI phy instance 2 byte clock
89 - description: HDMI phy PLL clock
120 const: qcom,mmcc-msm8994
125 - description: Board XO source
126 - description: Global PLL 0 clock
127 - description: MMSS NoC AHB clock
128 - description: GFX3D clock
129 - description: DSI phy instance 0 dsi clock
130 - description: DSI phy instance 0 byte clock
131 - description: DSI phy instance 1 dsi clock
132 - description: DSI phy instance 1 byte clock
133 - description: HDMI phy PLL clock
140 - const: oxili_gfx3d_clk_src
151 const: qcom,mmcc-msm8996
156 - description: Board XO source
157 - description: Global PLL 0 clock
158 - description: MMSS NoC AHB clock
159 - description: DSI phy instance 0 dsi clock
160 - description: DSI phy instance 0 byte clock
161 - description: DSI phy instance 1 dsi clock
162 - description: DSI phy instance 1 byte clock
163 - description: HDMI phy PLL clock
169 - const: gcc_mmss_noc_cfg_ahb_clk
180 const: qcom,mmcc-msm8998
185 - description: Board XO source
186 - description: Global PLL 0 clock
187 - description: DSI phy instance 0 dsi clock
188 - description: DSI phy instance 0 byte clock
189 - description: DSI phy instance 1 dsi clock
190 - description: DSI phy instance 1 byte clock
191 - description: HDMI phy PLL clock
192 - description: DisplayPort phy PLL link clock
193 - description: DisplayPort phy PLL vco clock
194 - description: Test clock
207 - const: core_bi_pll_test_se
220 - description: Board XO source
221 - description: Board sleep source
222 - description: Global PLL 0 clock
223 - description: Global PLL 0 DIV clock
224 - description: DSI phy instance 0 dsi clock
225 - description: DSI phy instance 0 byte clock
226 - description: DSI phy instance 1 dsi clock
227 - description: DSI phy instance 1 byte clock
228 - description: DisplayPort phy PLL link clock
229 - description: DisplayPort phy PLL vco clock
241 - const: dp_link_2x_clk_divsel_five
242 - const: dp_vco_divided_clk_src_mux
245 # Example for MMCC for MSM8960:
247 clock-controller@4000000 {
248 compatible = "qcom,mmcc-msm8960";
249 reg = <0x4000000 0x1000>;
252 #power-domain-cells = <1>;