1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm graphics clock control module which supports the clocks, resets and
14 power domains on SDM845/SC7180/SM8150/SM8250.
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sm8150.h
20 dt-bindings/clock/qcom,gpucc-sm8250.h
32 - description: Board XO source
33 - description: GPLL0 main branch source
34 - description: GPLL0 div branch source
39 - const: gcc_gpu_gpll0_clk_src
40 - const: gcc_gpu_gpll0_div_clk_src
48 '#power-domain-cells':
61 - '#power-domain-cells'
63 additionalProperties: false
67 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
68 #include <dt-bindings/clock/qcom,rpmh.h>
69 clock-controller@5090000 {
70 compatible = "qcom,sdm845-gpucc";
71 reg = <0x05090000 0x9000>;
72 clocks = <&rpmhcc RPMH_CXO_CLK>,
73 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
74 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
75 clock-names = "bi_tcxo",
76 "gcc_gpu_gpll0_clk_src",
77 "gcc_gpu_gpll0_div_clk_src";
80 #power-domain-cells = <1>;