1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm graphics clock control module which supports the clocks, resets and
14 power domains on Qualcomm SoCs.
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sc7280.h
20 dt-bindings/clock/qcom,gpucc-sc8280xp.h
21 dt-bindings/clock/qcom,gpucc-sm6350.h
22 dt-bindings/clock/qcom,gpucc-sm8150.h
23 dt-bindings/clock/qcom,gpucc-sm8250.h
39 - description: Board XO source
40 - description: GPLL0 main branch source
41 - description: GPLL0 div branch source
46 - const: gcc_gpu_gpll0_clk_src
47 - const: gcc_gpu_gpll0_div_clk_src
55 '#power-domain-cells':
68 - '#power-domain-cells'
70 additionalProperties: false
74 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
75 #include <dt-bindings/clock/qcom,rpmh.h>
76 clock-controller@5090000 {
77 compatible = "qcom,sdm845-gpucc";
78 reg = <0x05090000 0x9000>;
79 clocks = <&rpmhcc RPMH_CXO_CLK>,
80 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
81 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
82 clock-names = "bi_tcxo",
83 "gcc_gpu_gpll0_clk_src",
84 "gcc_gpu_gpll0_div_clk_src";
87 #power-domain-cells = <1>;