1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
15 power domains on SDM845
18 - dt-bindings/clock/qcom,gcc-sdm845.h
41 - $ref: qcom,gcc.yaml#
46 const: qcom,gcc-sdm670
51 - description: Board XO source
52 - description: Board active XO source
53 - description: Sleep clock source
64 const: qcom,gcc-sdm845
69 - description: Board XO source
70 - description: Board active XO source
71 - description: Sleep clock source
72 - description: PCIE 0 Pipe clock source
73 - description: PCIE 1 Pipe clock source
79 - const: pcie_0_pipe_clk
80 - const: pcie_1_pipe_clk
82 unevaluatedProperties: false
85 # Example for GCC for SDM845:
87 #include <dt-bindings/clock/qcom,rpmh.h>
88 clock-controller@100000 {
89 compatible = "qcom,gcc-sdm845";
90 reg = <0x100000 0x1f0000>;
91 clocks = <&rpmhcc RPMH_CXO_CLK>,
92 <&rpmhcc RPMH_CXO_CLK_A>,
96 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
99 #power-domain-cells = <1>;