Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Broadcom iProc Family Clocks
   8
   9 maintainers:
  10   - Ray Jui <rjui@broadcom.com>
  11   - Scott Branden <sbranden@broadcom.com>
  12
  13 description: |
  14   The iProc clock controller manages clocks that are common to the iProc family.
  15   An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
  16   LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
  17   comprises of several leaf clocks
  18
  19   ASIU clocks are a special case. These clocks are derived directly from the
  20   reference clock of the onboard crystal.
  21
  22 properties:
  23   compatible:
  24     enum:
  25       - brcm,bcm63138-armpll
  26       - brcm,cygnus-armpll
  27       - brcm,cygnus-genpll
  28       - brcm,cygnus-lcpll0
  29       - brcm,cygnus-mipipll
  30       - brcm,cygnus-asiu-clk
  31       - brcm,cygnus-audiopll
  32       - brcm,hr2-armpll
  33       - brcm,nsp-armpll
  34       - brcm,nsp-genpll
  35       - brcm,nsp-lcpll0
  36       - brcm,ns2-genpll-scr
  37       - brcm,ns2-genpll-sw
  38       - brcm,ns2-lcpll-ddr
  39       - brcm,ns2-lcpll-ports
  40       - brcm,sr-genpll0
  41       - brcm,sr-genpll1
  42       - brcm,sr-genpll2
  43       - brcm,sr-genpll3
  44       - brcm,sr-genpll4
  45       - brcm,sr-genpll5
  46       - brcm,sr-genpll6
  47       - brcm,sr-lcpll0
  48       - brcm,sr-lcpll1
  49       - brcm,sr-lcpll-pcie
  50
  51   reg:
  52     minItems: 1
  53     maxItems: 3
  54     items:
  55       - description: base register
  56       - description: power register
  57       - description: ASIU or split status register
  58
  59   clocks:
  60     description: The input parent clock phandle for the PLL / ASIU clock. For
  61       most iProc PLLs, this is an onboard crystal with a fixed rate.
  62     maxItems: 1
  63
  64   '#clock-cells':
  65     const: 1
  66
  67   clock-output-names:
  68     minItems: 1
  69     maxItems: 45
  70
  71 allOf:
  72   - if:
  73       properties:
  74         compatible:
  75           contains:
  76             enum:
  77               - brcm,cygnus-armpll
  78               - brcm,cygnus-genpll
  79               - brcm,cygnus-lcpll0
  80               - brcm,cygnus-mipipll
  81               - brcm,cygnus-asiu-clk
  82               - brcm,cygnus-audiopll
  83     then:
  84       properties:
  85         clock-output-names:
  86           description: |
  87             The following table defines the set of PLL/clock index and ID for Cygnus.
  88             These clock IDs are defined in:
  89                 "include/dt-bindings/clock/bcm-cygnus.h"
  90
  91             Clock       Source (Parent) Index   ID
  92             -----       --------------- -----   --
  93             crystal     N/A             N/A     N/A
  94
  95             armpll      crystal         N/A     N/A
  96
  97             keypad      crystal (ASIU)  0       BCM_CYGNUS_ASIU_KEYPAD_CLK
  98             adc/tsc     crystal (ASIU)  1       BCM_CYGNUS_ASIU_ADC_CLK
  99             pwm crystal (ASIU)          2       BCM_CYGNUS_ASIU_PWM_CLK
 100
 101             genpll      crystal         0       BCM_CYGNUS_GENPLL
 102             axi21       genpll          1       BCM_CYGNUS_GENPLL_AXI21_CLK
 103             250mhz      genpll          2       BCM_CYGNUS_GENPLL_250MHZ_CLK
 104             ihost_sys   genpll          3       BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
 105             enet_sw     genpll          4       BCM_CYGNUS_GENPLL_ENET_SW_CLK
 106             audio_125   genpll          5       BCM_CYGNUS_GENPLL_AUDIO_125_CLK
 107             can         genpll          6       BCM_CYGNUS_GENPLL_CAN_CLK
 108
 109             lcpll0      crystal         0       BCM_CYGNUS_LCPLL0
 110             pcie_phy    lcpll0          1       BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
 111             ddr_phy     lcpll0          2       BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
 112             sdio        lcpll0          3       BCM_CYGNUS_LCPLL0_SDIO_CLK
 113             usb_phy     lcpll0          4       BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
 114             smart_card  lcpll0          5       BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
 115             ch5_unused  lcpll0          6       BCM_CYGNUS_LCPLL0_CH5_UNUSED
 116
 117             mipipll     crystal         0       BCM_CYGNUS_MIPIPLL
 118             ch0_unused  mipipll         1       BCM_CYGNUS_MIPIPLL_CH0_UNUSED
 119             ch1_lcd     mipipll         2       BCM_CYGNUS_MIPIPLL_CH1_LCD
 120             ch2_v3d     mipipll         3       BCM_CYGNUS_MIPIPLL_CH2_V3D
 121             ch3_unused  mipipll         4       BCM_CYGNUS_MIPIPLL_CH3_UNUSED
 122             ch4_unused  mipipll         5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED
 123             ch5_unused  mipipll         6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED
 124
 125             audiopll    crystal         0       BCM_CYGNUS_AUDIOPLL
 126             ch0_audio   audiopll        1       BCM_CYGNUS_AUDIOPLL_CH0
 127             ch1_audio   audiopll        2       BCM_CYGNUS_AUDIOPLL_CH1
 128             ch2_audio   audiopll        3       BCM_CYGNUS_AUDIOPLL_CH2
 129   - if:
 130       properties:
 131         compatible:
 132           contains:
 133             enum:
 134               - brcm,hr2-armpll
 135     then:
 136       properties:
 137         clock-output-names:
 138           description: |
 139             The following table defines the set of PLL/clock for Hurricane 2:
 140
 141             Clock       Source          Index   ID
 142             -----       ------          -----   --
 143             crystal     N/A             N/A     N/A
 144
 145             armpll      crystal         N/A     N/A
 146   - if:
 147       properties:
 148         compatible:
 149           contains:
 150             enum:
 151               - brcm,nsp-armpll
 152               - brcm,nsp-genpll
 153               - brcm,nsp-lcpll0
 154     then:
 155       properties:
 156         clock-output-names:
 157           description: |
 158             The following table defines the set of PLL/clock index and ID for Northstar and
 159             Northstar Plus.  These clock IDs are defined in:
 160                 "include/dt-bindings/clock/bcm-nsp.h"
 161
 162             Clock       Source          Index   ID
 163             -----       ------          -----   --
 164             crystal     N/A             N/A     N/A
 165
 166             armpll      crystal         N/A     N/A
 167
 168             genpll      crystal         0       BCM_NSP_GENPLL
 169             phy         genpll          1       BCM_NSP_GENPLL_PHY_CLK
 170             ethernetclk genpll          2       BCM_NSP_GENPLL_ENET_SW_CLK
 171             usbclk      genpll          3       BCM_NSP_GENPLL_USB_PHY_REF_CLK
 172             iprocfast   genpll          4       BCM_NSP_GENPLL_IPROCFAST_CLK
 173             sata1       genpll          5       BCM_NSP_GENPLL_SATA1_CLK
 174             sata2       genpll          6       BCM_NSP_GENPLL_SATA2_CLK
 175
 176             lcpll0      crystal         0       BCM_NSP_LCPLL0
 177             pcie_phy    lcpll0          1       BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
 178             sdio        lcpll0          2       BCM_NSP_LCPLL0_SDIO_CLK
 179             ddr_phy     lcpll0          3       BCM_NSP_LCPLL0_DDR_PHY_CLK
 180   - if:
 181       properties:
 182         compatible:
 183           contains:
 184             enum:
 185               - brcm,ns2-genpll-scr
 186               - brcm,ns2-genpll-sw
 187               - brcm,ns2-lcpll-ddr
 188               - brcm,ns2-lcpll-ports
 189     then:
 190       properties:
 191         clock-output-names:
 192           description: |
 193             The following table defines the set of PLL/clock index and ID for Northstar 2.
 194             These clock IDs are defined in:
 195                 "include/dt-bindings/clock/bcm-ns2.h"
 196
 197             Clock       Source          Index   ID
 198             -----       ------          -----   --
 199             crystal     N/A             N/A     N/A
 200
 201             genpll_scr  crystal         0       BCM_NS2_GENPLL_SCR
 202             scr         genpll_scr      1       BCM_NS2_GENPLL_SCR_SCR_CLK
 203             fs          genpll_scr      2       BCM_NS2_GENPLL_SCR_FS_CLK
 204             audio_ref   genpll_scr      3       BCM_NS2_GENPLL_SCR_AUDIO_CLK
 205             ch3_unused  genpll_scr      4       BCM_NS2_GENPLL_SCR_CH3_UNUSED
 206             ch4_unused  genpll_scr      5       BCM_NS2_GENPLL_SCR_CH4_UNUSED
 207             ch5_unused  genpll_scr      6       BCM_NS2_GENPLL_SCR_CH5_UNUSED
 208
 209             genpll_sw   crystal         0       BCM_NS2_GENPLL_SW
 210             rpe         genpll_sw       1       BCM_NS2_GENPLL_SW_RPE_CLK
 211             250         genpll_sw       2       BCM_NS2_GENPLL_SW_250_CLK
 212             nic         genpll_sw       3       BCM_NS2_GENPLL_SW_NIC_CLK
 213             chimp       genpll_sw       4       BCM_NS2_GENPLL_SW_CHIMP_CLK
 214             port        genpll_sw       5       BCM_NS2_GENPLL_SW_PORT_CLK
 215             sdio        genpll_sw       6       BCM_NS2_GENPLL_SW_SDIO_CLK
 216
 217             lcpll_ddr   crystal         0       BCM_NS2_LCPLL_DDR
 218             pcie_sata_usb lcpll_ddr     1       BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
 219             ddr         lcpll_ddr       2       BCM_NS2_LCPLL_DDR_DDR_CLK
 220             ch2_unused  lcpll_ddr       3       BCM_NS2_LCPLL_DDR_CH2_UNUSED
 221             ch3_unused  lcpll_ddr       4       BCM_NS2_LCPLL_DDR_CH3_UNUSED
 222             ch4_unused  lcpll_ddr       5       BCM_NS2_LCPLL_DDR_CH4_UNUSED
 223             ch5_unused  lcpll_ddr       6       BCM_NS2_LCPLL_DDR_CH5_UNUSED
 224
 225             lcpll_ports crystal         0       BCM_NS2_LCPLL_PORTS
 226             wan         lcpll_ports     1       BCM_NS2_LCPLL_PORTS_WAN_CLK
 227             rgmii       lcpll_ports     2       BCM_NS2_LCPLL_PORTS_RGMII_CLK
 228             ch2_unused  lcpll_ports     3       BCM_NS2_LCPLL_PORTS_CH2_UNUSED
 229             ch3_unused  lcpll_ports     4       BCM_NS2_LCPLL_PORTS_CH3_UNUSED
 230             ch4_unused  lcpll_ports     5       BCM_NS2_LCPLL_PORTS_CH4_UNUSED
 231             ch5_unused  lcpll_ports     6       BCM_NS2_LCPLL_PORTS_CH5_UNUSED
 232   - if:
 233       properties:
 234         compatible:
 235           contains:
 236             enum:
 237               - brcm,sr-genpll0
 238               - brcm,sr-genpll1
 239               - brcm,sr-genpll2
 240               - brcm,sr-genpll3
 241               - brcm,sr-genpll4
 242               - brcm,sr-genpll5
 243               - brcm,sr-genpll6
 244               - brcm,sr-lcpll0
 245               - brcm,sr-lcpll1
 246               - brcm,sr-lcpll-pcie
 247     then:
 248       properties:
 249         clock-output-names:
 250           description: |
 251             The following table defines the set of PLL/clock index and ID for Stingray.
 252             These clock IDs are defined in:
 253                 "include/dt-bindings/clock/bcm-sr.h"
 254
 255             Clock               Source          Index   ID
 256             -----               ------          -----   --
 257             crystal             N/A             N/A     N/A
 258             crmu_ref25m         crystal         N/A     N/A
 259
 260             genpll0             crystal         0       BCM_SR_GENPLL0
 261             clk_125m            genpll0         1       BCM_SR_GENPLL0_125M_CLK
 262             clk_scr             genpll0         2       BCM_SR_GENPLL0_SCR_CLK
 263             clk_250             genpll0         3       BCM_SR_GENPLL0_250M_CLK
 264             clk_pcie_axi        genpll0         4       BCM_SR_GENPLL0_PCIE_AXI_CLK
 265             clk_paxc_axi_x2     genpll0         5       BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
 266             clk_paxc_axi        genpll0         6       BCM_SR_GENPLL0_PAXC_AXI_CLK
 267
 268             genpll1             crystal         0       BCM_SR_GENPLL1
 269             clk_pcie_tl         genpll1         1       BCM_SR_GENPLL1_PCIE_TL_CLK
 270             clk_mhb_apb         genpll1         2       BCM_SR_GENPLL1_MHB_APB_CLK
 271
 272             genpll2             crystal         0       BCM_SR_GENPLL2
 273             clk_nic             genpll2         1       BCM_SR_GENPLL2_NIC_CLK
 274             clk_ts_500_ref      genpll2         2       BCM_SR_GENPLL2_TS_500_REF_CLK
 275             clk_125_nitro       genpll2         3       BCM_SR_GENPLL2_125_NITRO_CLK
 276             clk_chimp           genpll2         4       BCM_SR_GENPLL2_CHIMP_CLK
 277             clk_nic_flash       genpll2         5       BCM_SR_GENPLL2_NIC_FLASH_CLK
 278             clk_fs              genpll2         6       BCM_SR_GENPLL2_FS_CLK
 279
 280             genpll3             crystal         0       BCM_SR_GENPLL3
 281             clk_hsls            genpll3         1       BCM_SR_GENPLL3_HSLS_CLK
 282             clk_sdio            genpll3         2       BCM_SR_GENPLL3_SDIO_CLK
 283
 284             genpll4             crystal         0       BCM_SR_GENPLL4
 285             clk_ccn             genpll4         1       BCM_SR_GENPLL4_CCN_CLK
 286             clk_tpiu_pll        genpll4         2       BCM_SR_GENPLL4_TPIU_PLL_CLK
 287             clk_noc             genpll4         3       BCM_SR_GENPLL4_NOC_CLK
 288             clk_chclk_fs4       genpll4         4       BCM_SR_GENPLL4_CHCLK_FS4_CLK
 289             clk_bridge_fscpu    genpll4         5       BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
 290
 291             genpll5             crystal         0       BCM_SR_GENPLL5
 292             clk_fs4_hf          genpll5         1       BCM_SR_GENPLL5_FS4_HF_CLK
 293             clk_crypto_ae       genpll5         2       BCM_SR_GENPLL5_CRYPTO_AE_CLK
 294             clk_raid_ae         genpll5         3       BCM_SR_GENPLL5_RAID_AE_CLK
 295
 296             genpll6             crystal         0       BCM_SR_GENPLL6
 297             clk_48_usb          genpll6         1       BCM_SR_GENPLL6_48_USB_CLK
 298
 299             lcpll0              crystal         0       BCM_SR_LCPLL0
 300             clk_sata_refp       lcpll0          1       BCM_SR_LCPLL0_SATA_REFP_CLK
 301             clk_sata_refn       lcpll0          2       BCM_SR_LCPLL0_SATA_REFN_CLK
 302             clk_sata_350        lcpll0          3       BCM_SR_LCPLL0_SATA_350_CLK
 303             clk_sata_500        lcpll0          4       BCM_SR_LCPLL0_SATA_500_CLK
 304
 305             lcpll1              crystal         0       BCM_SR_LCPLL1
 306             clk_wan             lcpll1          1       BCM_SR_LCPLL1_WAN_CLK
 307             clk_usb_ref         lcpll1          2       BCM_SR_LCPLL1_USB_REF_CLK
 308             clk_crmu_ts         lcpll1          3       BCM_SR_LCPLL1_CRMU_TS_CLK
 309
 310             lcpll_pcie          crystal         0       BCM_SR_LCPLL_PCIE
 311             clk_pcie_phy_ref    lcpll1          1       BCM_SR_LCPLL_PCIE_PHY_REF_CLK
 312   - if:
 313       properties:
 314         compatible:
 315           contains:
 316             const: brcm,cygnus-genpll
 317     then:
 318       properties:
 319         clock-output-names:
 320           items:
 321             - const: genpll
 322             - const: axi21
 323             - const: 250mhz
 324             - const: ihost_sys
 325             - const: enet_sw
 326             - const: audio_125
 327             - const: can
 328   - if:
 329       properties:
 330         compatible:
 331           contains:
 332             const: brcm,nsp-lcpll0
 333     then:
 334       properties:
 335         clock-output-names:
 336           items:
 337             - const: lcpll0
 338             - const: pcie_phy
 339             - const: sdio
 340             - const: ddr_phy
 341   - if:
 342       properties:
 343         compatible:
 344           contains:
 345             const: brcm,nsp-genpll
 346     then:
 347       properties:
 348         clock-output-names:
 349           items:
 350             - const: genpll
 351             - const: phy
 352             - const: ethernetclk
 353             - const: usbclk
 354             - const: iprocfast
 355             - const: sata1
 356             - const: sata2
 357
 358 required:
 359   - reg
 360   - clocks
 361   - '#clock-cells'
 362   - clock-output-names
 363
 364 additionalProperties: false
 365
 366 examples:
 367   - |
 368     osc1: oscillator {
 369         #clock-cells = <0>;
 370         compatible = "fixed-clock";
 371         clock-frequency = <25000000>;
 372     };
 373
 374     genpll@301d000 {
 375         #clock-cells = <1>;
 376         compatible = "brcm,cygnus-genpll";
 377         reg = <0x301d000 0x2c>, <0x301c020 0x4>;
 378         clocks = <&os1c>;
 379         clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
 380                      "enet_sw", "audio_125", "can";
 381     };
 382   - |
 383     osc2: oscillator {
 384         #clock-cells = <0>;
 385         compatible = "fixed-clock";
 386         clock-frequency = <25000000>;
 387     };
 388
 389     asiu_clks@301d048 {
 390         #clock-cells = <1>;
 391         compatible = "brcm,cygnus-asiu-clk";
 392         reg = <0x301d048 0xc>, <0x180aa024 0x4>;
 393         clocks = <&osc2>;
 394         clock-output-names = "keypad", "adc/touch", "pwm";
 395     };