Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
   8
   9 maintainers:
  10   - Liu Ying <victor.liu@nxp.com>
  11
  12 description: |
  13   i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
  14   sitting together with the PHYs.  It is not the same as the MSI bus coming
  15   from i.MX8 System Controller Unit (SCU) which is used to control power,
  16   clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
  17
  18   i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
  19   that is, MSI clock and AHB clock, need to be enabled so that peripherals
  20   connected to the bus can be accessed. Also, the bus is part of a power
  21   domain. The power domain needs to be enabled before the peripherals can
  22   be accessed.
  23
  24   Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
  25   like I2C controller, PWM controller, MIPI DSI controller and Control and
  26   Status Registers (CSR) module, are accessed through the bus.
  27
  28   The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
  29   pixel link MSI bus controller and does not allow SCFW user to control it.
  30   So, the controller's registers cannot be accessed by SCFW user. Hence,
  31   the interrupts generated by the controller don't make any sense from SCFW
  32   user's point of view.
  33
  34 allOf:
  35   - $ref: simple-pm-bus.yaml#
  36
  37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
  38 select:
  39   properties:
  40     compatible:
  41       contains:
  42         enum:
  43           - fsl,imx8qxp-display-pixel-link-msi-bus
  44           - fsl,imx8qm-display-pixel-link-msi-bus
  45   required:
  46     - compatible
  47
  48 properties:
  49   compatible:
  50     items:
  51       - enum:
  52           - fsl,imx8qxp-display-pixel-link-msi-bus
  53           - fsl,imx8qm-display-pixel-link-msi-bus
  54       - const: simple-pm-bus
  55
  56   reg:
  57     maxItems: 1
  58
  59   interrupts:
  60     maxItems: 1
  61
  62   clocks:
  63     items:
  64       - description: master gated clock from system
  65       - description: AHB clock
  66
  67   clock-names:
  68     items:
  69       - const: msi
  70       - const: ahb
  71
  72 patternProperties:
  73   "^.*@[0-9a-f]+$":
  74     description: Devices attached to the bus
  75     type: object
  76     properties:
  77       reg:
  78         maxItems: 1
  79
  80     required:
  81       - reg
  82
  83 required:
  84   - compatible
  85   - reg
  86   - clocks
  87   - clock-names
  88   - power-domains
  89
  90 unevaluatedProperties: false
  91
  92 examples:
  93   - |
  94     #include <dt-bindings/clock/imx8-lpcg.h>
  95     #include <dt-bindings/firmware/imx/rsrc.h>
  96     bus@56200000 {
  97         compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
  98         reg = <0x56200000 0x20000>;
  99         #address-cells = <1>;
 100         #size-cells = <1>;
 101         interrupt-parent = <&dc0_irqsteer>;
 102         interrupts = <320>;
 103         ranges;
 104         clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>,
 105                  <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>;
 106         clock-names = "msi", "ahb";
 107         power-domains = <&pd IMX_SC_R_DC_0>;
 108
 109         syscon@56221000 {
 110             compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
 111             reg = <0x56221000 0x1000>;
 112             clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
 113             clock-names = "ipg";
 114
 115             pxl2dpi {
 116                 compatible = "fsl,imx8qxp-pxl2dpi";
 117                 fsl,sc-resource = <IMX_SC_R_MIPI_0>;
 118                 power-domains = <&pd IMX_SC_R_MIPI_0>;
 119
 120                 ports {
 121                     #address-cells = <1>;
 122                     #size-cells = <0>;
 123
 124                     port@0 {
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                         reg = <0>;
 128
 129                         mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
 130                             reg = <0>;
 131                             remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
 132                         };
 133
 134                         mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
 135                             reg = <1>;
 136                             remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
 137                         };
 138                     };
 139
 140                     port@1 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         reg = <1>;
 144
 145                         mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
 146                             reg = <0>;
 147                             remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
 148                         };
 149
 150                         mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
 151                             reg = <1>;
 152                             remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
 153                         };
 154                     };
 155                 };
 156             };
 157
 158             ldb {
 159                 #address-cells = <1>;
 160                 #size-cells = <0>;
 161                 compatible = "fsl,imx8qxp-ldb";
 162                 clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
 163                          <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
 164                 clock-names = "pixel", "bypass";
 165                 power-domains = <&pd IMX_SC_R_LVDS_0>;
 166
 167                 channel@0 {
 168                     #address-cells = <1>;
 169                     #size-cells = <0>;
 170                     reg = <0>;
 171                     phys = <&mipi_lvds_0_phy>;
 172                     phy-names = "lvds_phy";
 173
 174                     port@0 {
 175                         reg = <0>;
 176
 177                         mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
 178                             remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
 179                         };
 180                     };
 181
 182                     port@1 {
 183                         reg = <1>;
 184
 185                         /* ... */
 186                     };
 187                 };
 188
 189                 channel@1 {
 190                     #address-cells = <1>;
 191                     #size-cells = <0>;
 192                     reg = <1>;
 193                     phys = <&mipi_lvds_0_phy>;
 194                     phy-names = "lvds_phy";
 195
 196                     port@0 {
 197                         reg = <0>;
 198
 199                         mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
 200                             remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
 201                         };
 202                     };
 203
 204                     port@1 {
 205                         reg = <1>;
 206
 207                         /* ... */
 208                     };
 209                 };
 210             };
 211         };
 212
 213         clock-controller@56223004 {
 214             compatible = "fsl,imx8qxp-lpcg";
 215             reg = <0x56223004 0x4>;
 216             #clock-cells = <1>;
 217             clocks = <&mipi_lvds_0_ipg_clk>;
 218             clock-indices = <IMX_LPCG_CLK_4>;
 219             clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk";
 220             power-domains = <&pd IMX_SC_R_MIPI_0>;
 221         };
 222
 223         phy@56228300 {
 224             compatible = "fsl,imx8qxp-mipi-dphy";
 225             reg = <0x56228300 0x100>;
 226             clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
 227             clock-names = "phy_ref";
 228             #phy-cells = <0>;
 229             fsl,syscon = <&mipi_lvds_0_csr>;
 230             power-domains = <&pd IMX_SC_R_MIPI_0>;
 231         };
 232     };