1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w
25 - mediatek,mt8192-imp_iic_wrap_n
26 - mediatek,mt8192-msdc_top
27 - mediatek,mt8192-msdc
28 - mediatek,mt8192-mfgcfg
29 - mediatek,mt8192-imgsys
30 - mediatek,mt8192-imgsys2
31 - mediatek,mt8192-vdecsys_soc
32 - mediatek,mt8192-vdecsys
33 - mediatek,mt8192-vencsys
34 - mediatek,mt8192-camsys
35 - mediatek,mt8192-camsys_rawa
36 - mediatek,mt8192-camsys_rawb
37 - mediatek,mt8192-camsys_rawc
38 - mediatek,mt8192-ipesys
39 - mediatek,mt8192-mdpsys
51 additionalProperties: false
55 scp_adsp: clock-controller@10720000 {
56 compatible = "mediatek,mt8192-scp_adsp";
57 reg = <0x10720000 0x1000>;
62 imp_iic_wrap_c: clock-controller@11007000 {
63 compatible = "mediatek,mt8192-imp_iic_wrap_c";
64 reg = <0x11007000 0x1000>;
69 imp_iic_wrap_e: clock-controller@11cb1000 {
70 compatible = "mediatek,mt8192-imp_iic_wrap_e";
71 reg = <0x11cb1000 0x1000>;
76 imp_iic_wrap_s: clock-controller@11d03000 {
77 compatible = "mediatek,mt8192-imp_iic_wrap_s";
78 reg = <0x11d03000 0x1000>;
83 imp_iic_wrap_ws: clock-controller@11d23000 {
84 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
85 reg = <0x11d23000 0x1000>;
90 imp_iic_wrap_w: clock-controller@11e01000 {
91 compatible = "mediatek,mt8192-imp_iic_wrap_w";
92 reg = <0x11e01000 0x1000>;
97 imp_iic_wrap_n: clock-controller@11f02000 {
98 compatible = "mediatek,mt8192-imp_iic_wrap_n";
99 reg = <0x11f02000 0x1000>;
104 msdc_top: clock-controller@11f10000 {
105 compatible = "mediatek,mt8192-msdc_top";
106 reg = <0x11f10000 0x1000>;
111 msdc: clock-controller@11f60000 {
112 compatible = "mediatek,mt8192-msdc";
113 reg = <0x11f60000 0x1000>;
118 mfgcfg: clock-controller@13fbf000 {
119 compatible = "mediatek,mt8192-mfgcfg";
120 reg = <0x13fbf000 0x1000>;
125 imgsys: clock-controller@15020000 {
126 compatible = "mediatek,mt8192-imgsys";
127 reg = <0x15020000 0x1000>;
132 imgsys2: clock-controller@15820000 {
133 compatible = "mediatek,mt8192-imgsys2";
134 reg = <0x15820000 0x1000>;
139 vdecsys_soc: clock-controller@1600f000 {
140 compatible = "mediatek,mt8192-vdecsys_soc";
141 reg = <0x1600f000 0x1000>;
146 vdecsys: clock-controller@1602f000 {
147 compatible = "mediatek,mt8192-vdecsys";
148 reg = <0x1602f000 0x1000>;
153 vencsys: clock-controller@17000000 {
154 compatible = "mediatek,mt8192-vencsys";
155 reg = <0x17000000 0x1000>;
160 camsys: clock-controller@1a000000 {
161 compatible = "mediatek,mt8192-camsys";
162 reg = <0x1a000000 0x1000>;
167 camsys_rawa: clock-controller@1a04f000 {
168 compatible = "mediatek,mt8192-camsys_rawa";
169 reg = <0x1a04f000 0x1000>;
174 camsys_rawb: clock-controller@1a06f000 {
175 compatible = "mediatek,mt8192-camsys_rawb";
176 reg = <0x1a06f000 0x1000>;
181 camsys_rawc: clock-controller@1a08f000 {
182 compatible = "mediatek,mt8192-camsys_rawc";
183 reg = <0x1a08f000 0x1000>;
188 ipesys: clock-controller@1b000000 {
189 compatible = "mediatek,mt8192-ipesys";
190 reg = <0x1b000000 0x1000>;
195 mdpsys: clock-controller@1f000000 {
196 compatible = "mediatek,mt8192-mdpsys";
197 reg = <0x1f000000 0x1000>;