1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
120 - arm,armv8 # Only for s/w models
164 - nvidia,tegra132-denver
165 - nvidia,tegra186-denver
166 - nvidia,tegra194-carmel
180 $ref: '/schemas/types.yaml#/definitions/string'
182 # On ARM v8 64-bit this property is required
186 # On ARM 32-bit systems this property is optional
189 - allwinner,sun6i-a31
190 - allwinner,sun8i-a23
191 - allwinner,sun9i-a80-smp
192 - allwinner,sun8i-a83t-smp
194 - amlogic,meson8b-smp
197 - brcm,bcm11351-cpu-method
203 - marvell,armada-375-smp
204 - marvell,armada-380-smp
205 - marvell,armada-390-smp
206 - marvell,armada-xp-smp
207 - marvell,98dx3236-smp
209 - mediatek,mt6589-smp
210 - mediatek,mt81xx-tz-smp
215 - renesas,r9a06g032-smp
216 - rockchip,rk3036-smp
217 - rockchip,rk3066-smp
218 - socionext,milbeaut-m10v-smp
224 $ref: '/schemas/types.yaml#/definitions/uint64'
227 Required for systems that have an "enable-method"
228 property value of "spin-table".
229 On ARM v8 64-bit systems must be a two cell
230 property identifying a 64-bit zero-initialised
234 $ref: '/schemas/types.yaml#/definitions/phandle-array'
236 List of phandles to idle state nodes supported
237 by this cpu (see ./idle-states.yaml).
241 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
242 DMIPS/MHz, relative to highest capacity-dmips-mhz
245 cci-control-port: true
247 dynamic-power-coefficient:
248 $ref: '/schemas/types.yaml#/definitions/uint32'
250 A u32 value that represents the running time dynamic
251 power coefficient in units of uW/MHz/V^2. The
252 coefficient can either be calculated from power
253 measurements or derived by analysis.
255 The dynamic power consumption of the CPU is
256 proportional to the square of the Voltage (V) and
257 the clock frequency (f). The coefficient is used to
258 calculate the dynamic power as below -
260 Pdyn = dynamic-power-coefficient * V^2 * f
262 where voltage is in V, frequency is in MHz.
267 List of phandles and performance domain specifiers, as defined by
268 bindings of the performance domain provider. See also
269 dvfs/performance-domain.yaml.
273 List of phandles and PM domain specifiers, as defined by bindings of the
274 PM domain provider (see also ../power_domain.txt).
278 A list of power domain name strings sorted in the same order as the
279 power-domains property.
281 For PSCI based platforms, the name corresponding to the index of the PSCI
282 PM domain provider, must be "psci".
285 $ref: '/schemas/types.yaml#/definitions/phandle'
287 Specifies the SAW* node associated with this CPU.
289 Required for systems that have an "enable-method" property
290 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
292 * arm/msm/qcom,saw2.txt
295 $ref: '/schemas/types.yaml#/definitions/phandle'
297 Specifies the ACC* node associated with this CPU.
299 Required for systems that have an "enable-method" property
300 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
302 * arm/msm/qcom,kpss-acc.txt
305 $ref: '/schemas/types.yaml#/definitions/phandle'
307 Specifies the syscon node controlling the cpu core power domains.
309 Optional for systems that have an "enable-method"
310 property value of "rockchip,rk3066-smp"
311 While optional, it is the preferred way to get access to
312 the cpu-core power-domains.
315 $ref: '/schemas/types.yaml#/definitions/uint32'
317 Required for systems that have an "enable-method" property value of
318 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
320 This includes the following SoCs: |
321 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
322 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
324 The secondary-boot-reg property is a u32 value that specifies the
325 physical address of the register used to request the ROM holding pen
326 code release a secondary CPU. The value written to the register is
327 formed by encoding the target CPU id into the low bits of the
328 physical start address it should jump to.
331 # If the enable-method property contains one of those values
336 - brcm,bcm11351-cpu-method
339 # and if enable-method is present
353 rockchip,pmu: [enable-method]
355 additionalProperties: true
361 #address-cells = <1>;
365 compatible = "arm,cortex-a15";
371 compatible = "arm,cortex-a15";
377 compatible = "arm,cortex-a7";
383 compatible = "arm,cortex-a7";
389 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
392 #address-cells = <1>;
396 compatible = "arm,cortex-a8";
402 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
405 #address-cells = <1>;
409 compatible = "arm,arm926ej-s";
415 // Example 4 (ARM Cortex-A57 64-bit system):
418 #address-cells = <2>;
422 compatible = "arm,cortex-a57";
424 enable-method = "spin-table";
425 cpu-release-addr = <0 0x20000000>;
430 compatible = "arm,cortex-a57";
432 enable-method = "spin-table";
433 cpu-release-addr = <0 0x20000000>;
438 compatible = "arm,cortex-a57";
440 enable-method = "spin-table";
441 cpu-release-addr = <0 0x20000000>;
446 compatible = "arm,cortex-a57";
448 enable-method = "spin-table";
449 cpu-release-addr = <0 0x20000000>;
454 compatible = "arm,cortex-a57";
456 enable-method = "spin-table";
457 cpu-release-addr = <0 0x20000000>;
462 compatible = "arm,cortex-a57";
464 enable-method = "spin-table";
465 cpu-release-addr = <0 0x20000000>;
470 compatible = "arm,cortex-a57";
472 enable-method = "spin-table";
473 cpu-release-addr = <0 0x20000000>;
478 compatible = "arm,cortex-a57";
480 enable-method = "spin-table";
481 cpu-release-addr = <0 0x20000000>;
486 compatible = "arm,cortex-a57";
488 enable-method = "spin-table";
489 cpu-release-addr = <0 0x20000000>;
494 compatible = "arm,cortex-a57";
496 enable-method = "spin-table";
497 cpu-release-addr = <0 0x20000000>;
502 compatible = "arm,cortex-a57";
504 enable-method = "spin-table";
505 cpu-release-addr = <0 0x20000000>;
510 compatible = "arm,cortex-a57";
512 enable-method = "spin-table";
513 cpu-release-addr = <0 0x20000000>;
518 compatible = "arm,cortex-a57";
520 enable-method = "spin-table";
521 cpu-release-addr = <0 0x20000000>;
526 compatible = "arm,cortex-a57";
528 enable-method = "spin-table";
529 cpu-release-addr = <0 0x20000000>;
534 compatible = "arm,cortex-a57";
536 enable-method = "spin-table";
537 cpu-release-addr = <0 0x20000000>;
542 compatible = "arm,cortex-a57";
544 enable-method = "spin-table";
545 cpu-release-addr = <0 0x20000000>;